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1 Ergebnisse
1
WRIP : logic restructuring techniques for wirelength-dri..:
, In:
Proceedings of the great lakes symposium on VLSI
,
Wei, Xing
;
Tang, Wai-Chung
;
Wu, Yu-Liang
.. - p. 327-332 , 2012
Link:
https://dl.acm.org/doi/10.1145/2206781.2206861
RT T1 <cTitle>Proceedings of the great lakes symposium on VLSI</cTitle>: T1 <Title>WRIP : logic restructuring techniques for wirelength-driven incremental placement</Title> UL https://suche.suub.uni-bremen.de/peid=acm-2206861&Exemplar=1&LAN=DE A1 Wei, Xing A1 Tang, Wai-Chung A1 Wu, Yu-Liang A1 Sze, Cliff A1 Alpert, Charles PB ACM YR 2012 K1 HPWL K1 incremental placement K1 logic rewiring K1 wirelength driven K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Logic synthesis K1 Circuit optimization SP 327 OP 332 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2206781.2206861 DO https://dl.acm.org/doi/10.1145/2206781.2206861 SF ELIB - SuUB Bremen
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