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1
Speeding up pipelined circuits through a combination of gat..:
, In:
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
,
Sathyamurthy, Harsha
;
Sapatnekar, Sachin S.
;
Fishburn, John P.
- p. 467-470 , 1995
Link:
https://dl.acm.org/doi/10.5555/224841.225092
RT T1 <cTitle>Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design</cTitle>: T1 <Title>Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization</Title> UL https://suche.suub.uni-bremen.de/peid=acm-225092&Exemplar=1&LAN=DE A1 Sathyamurthy, Harsha A1 Sapatnekar, Sachin S. A1 Fishburn, John P. PB IEEE Computer Society YR 1995 K1 acyclic pipelines K1 area-delay tradeoff K1 circuit CAD K1 circuit optimisation K1 clock skew optimization K1 combinational circuits K1 cycle-borrowing K1 gate sizing K1 logic CAD K1 logic design K1 logic gates K1 pipeline processing K1 pipelined circuits K1 timing specifications K1 Hardware K1 Electronic design automation K1 Logic synthesis K1 Circuit optimization SP 467 OP 470 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/224841.225092 DO https://dl.acm.org/doi/10.5555/224841.225092 SF ELIB - SuUB Bremen
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