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1 Ergebnisse
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Memory Latency Hiding by Load Value Speculation for Reconfi..:
Thielmann, Benjamin
;
Huthmann, Jens
;
Koch, Andreas
ACM Transactions on Reconfigurable Technology and Systems (TRETS). 5 (2012) 3 - p. 1-14 , 2012
Link:
https://dl.acm.org/doi/10.1145/2362374.2362377
RT Journal T1 <Title>Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers</Title> UL https://suche.suub.uni-bremen.de/peid=acm-2362377&Exemplar=1&LAN=DE A1 Thielmann, Benjamin A1 Huthmann, Jens A1 Koch, Andreas PB ACM YR 2012 SN 1936-7406 SN 1936-7414 K1 FPGA K1 high-level language compilation K1 memory interface K1 speculative execution K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Hardware-software codesign K1 Datapath optimization K1 Computer systems organization K1 Architectures K1 Other architectures K1 Self-organizing autonomic computing K1 Heterogeneous (hybrid) systems K1 Reconfigurable computing JF ACM Transactions on Reconfigurable Technology and Systems (TRETS) VO 5 IS 3 SP 1 OP 14 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2362374.2362377 DO https://dl.acm.org/doi/10.1145/2362374.2362377 SF ELIB - SuUB Bremen
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