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1 Ergebnisse
1
XPoint cache : scaling existing bus-based coherence prot..:
, In:
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
,
Dreslinski, Ronald G.
;
Manville, Thomas
;
Sewell, Korey
... - p. 75-86 , 2012
Link:
https://dl.acm.org/doi/10.1145/2370816.2370829
RT T1
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
: T1
XPoint cache : scaling existing bus-based coherence protocols for 2D and 3D many-core systems
UL https://suche.suub.uni-bremen.de/peid=acm-2370829&Exemplar=1&LAN=DE A1 Dreslinski, Ronald G. A1 Manville, Thomas A1 Sewell, Korey A1 Das, Reetuparna A1 Pinckney, Nathaniel A1 Satpathy, Sudhir A1 Blaauw, David A1 Sylvester, Dennis A1 Mudge, Trevor PB ACM YR 2012 K1 3D integration K1 bus design K1 cache coherence K1 interconnect K1 Hardware K1 Computer systems organization SP 75 OP 86 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2370816.2370829 DO https://dl.acm.org/doi/10.1145/2370816.2370829 SF ELIB - SuUB Bremen
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