I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
A case of system-level hardware/software co-design and co-v..:
, In:
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
,
Hong, Sungpack
;
Oguntebi, Tayo
;
Casper, Jared
... - p. 513-520 , 2012
Link:
https://dl.acm.org/doi/10.1145/2380445.2380524
RT T1
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
: T1
A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware
UL https://suche.suub.uni-bremen.de/peid=acm-2380524&Exemplar=1&LAN=DE A1 Hong, Sungpack A1 Oguntebi, Tayo A1 Casper, Jared A1 Bronson, Nathan A1 Kozyrakis, Christos A1 Olukotun, Kunle PB ACM YR 2012 K1 bus functional model K1 co-simulation K1 co-verification K1 fpga prototyping K1 transactional memory K1 Hardware K1 Hardware test K1 Test-pattern generation and fault simulation K1 Hardware validation K1 Functional verification SP 513 OP 520 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2380445.2380524 DO https://dl.acm.org/doi/10.1145/2380445.2380524 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)