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Optimization of custom MOS circuits by transistor sizing:
, In:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
,
Conn, Andrew R.
;
Coulman, Paula K.
;
Haring, Ruud A.
.. - p. 174-180 , 1997
Link:
https://dl.acm.org/doi/10.5555/244522.244551
RT T1
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
: T1
Optimization of custom MOS circuits by transistor sizing
UL https://suche.suub.uni-bremen.de/peid=acm-244551&Exemplar=1&LAN=DE A1 Conn, Andrew R. A1 Coulman, Paula K. A1 Haring, Ruud A. A1 Morrill, Gregory L. A1 Visweswariah, Chandu PB IEEE Computer Society YR 1997 K1 Circuits K1 gradients. K1 optimization K1 simulation K1 transistor sizing K1 Hardware K1 Integrated circuits K1 Hardware test K1 Electronic design automation K1 Physical design (EDA) K1 Robustness K1 Hardware reliability SP 174 OP 180 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/244522.244551 DO https://dl.acm.org/doi/10.5555/244522.244551 SF ELIB - SuUB Bremen
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