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1 Ergebnisse
1
Vertically-stacked double-gate nanowire FETs with controlla..:
, In:
Proceedings of the Conference on Design, Automation and Test in Europe
,
Gaillardon, Pierre-Emmanuel
;
Amarù, Luca Gaetano
;
Bobba, Shashikanth
... - p. 625-630 , 2013
Link:
https://dl.acm.org/doi/10.5555/2485288.2485442
RT T1 <cTitle>Proceedings of the Conference on Design, Automation and Test in Europe</cTitle>: T1 <Title>Vertically-stacked double-gate nanowire FETs with controllable polarity : from devices to regular ASICs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-2485442&Exemplar=1&LAN=DE A1 Gaillardon, Pierre-Emmanuel A1 Amarù, Luca Gaetano A1 Bobba, Shashikanth A1 De Marchi, Michele A1 Sacchetto, Davide A1 Leblebici, Yusuf A1 De Micheli, Giovanni PB EDA Consortium YR 2013 K1 XOR logic synthesis K1 controllable polarity K1 nanowire transistors K1 regular fabrics K1 Hardware K1 Emerging technologies K1 Very large scale integration design K1 Hardware validation K1 Electronic design automation K1 Physical design (EDA) SP 625 OP 630 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2485288.2485442 DO https://dl.acm.org/doi/10.5555/2485288.2485442 SF ELIB - SuUB Bremen
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