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A critical-section-level timing synchronization approach fo..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,

Yu, Fan-Wei ; Zeng, Bo-Han ; Huang, Yu-Hung... - p. 643-648 , 2013

Link: https://dl.acm.org/doi/10.5555/2485288.2485446

RT 
T1 <cTitle>Proceedings of the Conference on Design, Automation and Test in Europe</cTitle>: T1 <Title>A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-2485446&Exemplar=1&LAN=DE
				
A1 Yu, Fan-Wei
A1 Zeng, Bo-Han
A1 Huang, Yu-Hung
A1 Wu, Hsin-I
A1 Lee, Che-Rung
A1 Tsay, Ren-Song
PB EDA Consortium
YR 2013
K1 deterministic
K1 multi-core instruction-set simulations
K1 timing synchronization
K1 Hardware
K1 Very large scale integration design
K1 Application-specific VLSI designs
K1 Application specific instruction set processors
K1 Computer systems organization
K1 Architectures
K1 Serial architectures
K1 Reduced instruction set computing
K1 Parallel architectures
K1 Very long instruction word
K1 Complex instruction set computing
SP 643
OP 648
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2485288.2485446
DO https://dl.acm.org/doi/10.5555/2485288.2485446
SF ELIB - SuUB Bremen

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