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1 Ergebnisse
1
Co-synthesis of data paths and clock control paths for mini..:
, In:
Proceedings of the Conference on Design, Automation and Test in Europe
,
Tu, Wen-Pin
;
Huang, Shih-Hsu
;
Cheng, Chun-Hua
- p. 1831-1836 , 2013
Link:
https://dl.acm.org/doi/10.5555/2485288.2485720
RT T1
Proceedings of the Conference on Design, Automation and Test in Europe
: T1
Co-synthesis of data paths and clock control paths for minimum-period clock gating
UL https://suche.suub.uni-bremen.de/peid=acm-2485720&Exemplar=1&LAN=DE A1 Tu, Wen-Pin A1 Huang, Shih-Hsu A1 Cheng, Chun-Hua PB EDA Consortium YR 2013 K1 clock gating K1 clock period minimization K1 data path synthesis K1 delay insertion K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Datapath optimization K1 Hardware validation SP 1831 OP 1836 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2485288.2485720 DO https://dl.acm.org/doi/10.5555/2485288.2485720 SF ELIB - SuUB Bremen
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