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1 Ergebnisse
1
XDRA : exploration and optimization of last-level cache ..:
, In:
Proceedings of the 50th Annual Design Automation Conference
,
Min, Su Myat
;
Javaid, Haris
;
Parameswaran, Sri
- p. 1-10 , 2013
Link:
https://dl.acm.org/doi/10.1145/2463209.2488761
RT T1
Proceedings of the 50th Annual Design Automation Conference
: T1
XDRA : exploration and optimization of last-level cache for energy reduction in DDR DRAMs
UL https://suche.suub.uni-bremen.de/peid=acm-2488761&Exemplar=1&LAN=DE A1 Min, Su Myat A1 Javaid, Haris A1 Parameswaran, Sri PB ACM YR 2013 K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory K1 Hardware validation SP 1 OP 10 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2463209.2488761 DO https://dl.acm.org/doi/10.1145/2463209.2488761 SF ELIB - SuUB Bremen
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