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A framework for simulating hybrid MTJ/CMOS circuits : at..:
, In:
Proceedings of the Conference on Design, Automation and Test in Europe
,
Panagopoulos, Georgios
;
Augustine, Charles
;
Roy, Kaushik
- p. 1443-1446 , 2012
Link:
https://dl.acm.org/doi/10.5555/2492708.2493061
RT T1
Proceedings of the Conference on Design, Automation and Test in Europe
: T1
A framework for simulating hybrid MTJ/CMOS circuits : atoms to system approach
UL https://suche.suub.uni-bremen.de/peid=acm-2493061&Exemplar=1&LAN=DE A1 Panagopoulos, Georgios A1 Augustine, Charles A1 Roy, Kaushik PB EDA Consortium YR 2012 K1 LLG K1 MTJ K1 SPICE K1 STT-MRAM K1 simulation framework K1 Hardware K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Emerging technologies K1 Very large scale integration design K1 Computing methodologies K1 Modeling and simulation K1 Simulation support systems SP 1443 OP 1446 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2492708.2493061 DO https://dl.acm.org/doi/10.5555/2492708.2493061 SF ELIB - SuUB Bremen
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