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1 Ergebnisse
1
Multi-patch generation for multi-error logic rectification ..:
, In:
Proceedings of the Conference on Design, Automation and Test in Europe
,
Tang, Kai-Fu
;
Huang, Po-Kai
;
Chou, Chun-Nan
. - p. 1567-1572 , 2012
Link:
https://dl.acm.org/doi/10.5555/2492708.2493091
RT T1
Proceedings of the Conference on Design, Automation and Test in Europe
: T1
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
UL https://suche.suub.uni-bremen.de/peid=acm-2493091&Exemplar=1&LAN=DE A1 Tang, Kai-Fu A1 Huang, Po-Kai A1 Chou, Chun-Nan A1 Huang, Chung-Yang (Ric) PB EDA Consortium YR 2012 K1 Hardware K1 Integrated circuits K1 Logic circuits K1 Arithmetic and datapath circuits K1 Hardware test K1 Robustness K1 Hardware validation SP 1567 OP 1572 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2492708.2493091 DO https://dl.acm.org/doi/10.5555/2492708.2493091 SF ELIB - SuUB Bremen
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