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1 Ergebnisse
1
Power optimization for clock network with clock gate clonin..:
, In:
Proceedings of the 2014 on International symposium on physical design
,
Lo, Shih-Chuan
;
Hsu, Chih-Cheng
;
Lin, Mark Po-Hung
- p. 77-84 , 2014
Link:
https://dl.acm.org/doi/10.1145/2560519.2560520
RT T1
Proceedings of the 2014 on International symposium on physical design
: T1
Power optimization for clock network with clock gate cloning and flip-flop merging
UL https://suche.suub.uni-bremen.de/peid=acm-2560520&Exemplar=1&LAN=DE A1 Lo, Shih-Chuan A1 Hsu, Chih-Cheng A1 Lin, Mark Po-Hung PB ACM YR 2014 K1 clock gating K1 clock network K1 multi-bit flip-flop K1 power optimization K1 Hardware K1 Electronic design automation K1 Physical design (EDA) K1 Placement K1 Wire routing SP 77 OP 84 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2560519.2560520 DO https://dl.acm.org/doi/10.1145/2560519.2560520 SF ELIB - SuUB Bremen
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