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1 Ergebnisse
1
OCV-aware top-level clock tree optimization:
, In:
Proceedings of the 24th edition of the great lakes symposium on VLSI
,
Chan, Tuck-Boon
;
Han, Kwangsoo
;
Kahng, Andrew B.
.. - p. 33-38 , 2014
Link:
https://dl.acm.org/doi/10.1145/2591513.2591541
RT T1
Proceedings of the 24th edition of the great lakes symposium on VLSI
: T1
OCV-aware top-level clock tree optimization
UL https://suche.suub.uni-bremen.de/peid=acm-2591541&Exemplar=1&LAN=DE A1 Chan, Tuck-Boon A1 Han, Kwangsoo A1 Kahng, Andrew B. A1 Lee, Jae-Gon A1 Nath, Siddhartha PB ACM YR 2014 K1 buffer insertion K1 clock logic cells K1 clock tree synthesis K1 top-level clock tree K1 Hardware K1 Electronic design automation K1 Physical design (EDA) K1 Placement K1 Wire routing SP 33 OP 38 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2591513.2591541 DO https://dl.acm.org/doi/10.1145/2591513.2591541 SF ELIB - SuUB Bremen
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