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1 Ergebnisse
1
Area minimization synthesis for reconfigurable single-elect..:
, In:
Proceedings of the conference on Design, Automation & Test in Europe
,
Chen, Yi-Hang
;
Chen, Jian-Yu
;
Huang, Juinn-Dar
- p. 1-4 , 2014
Link:
https://dl.acm.org/doi/10.5555/2616606.2616756
RT T1
Proceedings of the conference on Design, Automation & Test in Europe
: T1
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints
UL https://suche.suub.uni-bremen.de/peid=acm-2616756&Exemplar=1&LAN=DE A1 Chen, Yi-Hang A1 Chen, Jian-Yu A1 Huang, Juinn-Dar PB European Design and Automation Association YR 2014 K1 area minimization K1 automatic synthesis K1 binary decision diagram K1 reconfigurable K1 single-electron transistor K1 Applied computing K1 Physical sciences and engineering K1 Electronics K1 Hardware K1 Integrated circuits K1 Robustness SP 1 OP 4 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2616606.2616756 DO https://dl.acm.org/doi/10.5555/2616606.2616756 SF ELIB - SuUB Bremen
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