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Graph-Based Approaches to Placement of Processing Element N..:
Miller, Bailey
;
Vahid, Frank
;
Givargis, Tony
.
ACM Transactions on Reconfigurable Technology and Systems (TRETS). 7 (2014) 4 - p. 1-22 , 2014
Link:
https://dl.acm.org/doi/10.1145/2629521
RT Journal T1
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation
UL https://suche.suub.uni-bremen.de/peid=acm-2629521&Exemplar=1&LAN=DE A1 Miller, Bailey A1 Vahid, Frank A1 Givargis, Tony A1 Brisk, Philip PB ACM YR 2014 SN 1936-7406 SN 1936-7414 K1 Field programmable gate array (FPGA) K1 cyber-physical system K1 differential equation K1 graph embedding K1 physical model K1 placement K1 simulated annealing K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Computer systems organization K1 Real-time systems K1 Embedded and cyber-physical systems JF ACM Transactions on Reconfigurable Technology and Systems (TRETS) VO 7 IS 4 SP 1 OP 22 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2629521 DO https://dl.acm.org/doi/10.1145/2629521 SF ELIB - SuUB Bremen
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