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Converting thread-level parallelism to instruction-level pa..:

Lo, Jack L. ; Emer, Joel S. ; Levy, Henry M....
ACM Transactions on Computer Systems (TOCS). 15 (1997) 3 - p. 322-354 , 1997

Link: https://dl.acm.org/doi/10.1145/263326.263382

RT Journal
T1 <Title>Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-263382&Exemplar=1&LAN=DE
				
A1 Lo, Jack L.
A1 Emer, Joel S.
A1 Levy, Henry M.
A1 Stamm, Rebecca L.
A1 Tullsen, Dean M.
A1 Eggers, S. J.
PB ACM
YR 1997
SN 0734-2071
SN 1557-7333
K1 cache interference
K1 instruction-level parallelism
K1 multiprocessors
K1 multithreading
K1 simultaneous multithreading
K1 thread-level parallelism
K1 Computer systems organization
K1 Architectures
K1 Parallel architectures
K1 Serial architectures
K1 Reduced instruction set computing
K1 Very long instruction word
K1 Software and its engineering
K1 Software organization and properties
K1 Contextual software domains
K1 Operating systems
K1 Process management
K1 Complex instruction set computing
JF ACM Transactions on Computer Systems (TOCS)
VO 15
IS 3
SP 322
OP 354
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/263326.263382
DO https://dl.acm.org/doi/10.1145/263326.263382
SF ELIB - SuUB Bremen

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