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A task-level hierarchical memory model for system synthesis..:

, In: Proceedings of the 34th annual Design Automation Conference,

Li, Yanbing ; Wolf, Wayne - p. 153-156 , 1997

Link: https://dl.acm.org/doi/10.1145/266021.266053

RT 
T1 <cTitle>Proceedings of the 34th annual Design Automation Conference</cTitle>: T1 <Title>A task-level hierarchical memory model for system synthesis of multiprocessors</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-266053&Exemplar=1&LAN=DE
				
A1 Li, Yanbing
A1 Wolf, Wayne
PB ACM
YR 1997
K1 Networks
K1 Network performance evaluation
K1 Computer systems organization
K1 Dependable and fault-tolerant systems and networks
K1 General and reference
K1 Cross-computing tools and techniques
K1 Performance
K1 Architectures
K1 Parallel architectures
K1 Multiple instruction, multiple data
K1 Theory of computation
K1 Theory and algorithms for application domains
K1 Machine learning theory
K1 Reinforcement learning
K1 Sequential decision making
K1 Design and analysis of algorithms
K1 Online algorithms
K1 Online learning algorithms
K1 Scheduling algorithms
K1 Hardware
K1 Integrated circuits
K1 Semiconductor memory
K1 Approximation algorithms analysis
SP 153
OP 156
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/266021.266053
DO https://dl.acm.org/doi/10.1145/266021.266053
SF ELIB - SuUB Bremen

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