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Forward model checking techniques oriented to buggy designs:
, In:
Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
,
Iwashita, Hiroaki
;
Nakata, Tsuneo
- p. 400-404 , 1997
Link:
https://dl.acm.org/doi/10.5555/266388.266515
RT T1 <cTitle>Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design</cTitle>: T1 <Title>Forward model checking techniques oriented to buggy designs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-266515&Exemplar=1&LAN=DE A1 Iwashita, Hiroaki A1 Nakata, Tsuneo PB IEEE Computer Society YR 1997 K1 formal verification K1 forward model checking K1 symbolic model checking K1 symbolic state traversal K1 Hardware K1 Integrated circuits K1 Logic circuits K1 Sequential circuits K1 General and reference K1 Cross-computing tools and techniques K1 Performance K1 Hardware test K1 Robustness K1 Hardware reliability K1 Networks K1 Network performance evaluation K1 Computer systems organization K1 Dependable and fault-tolerant systems and networks SP 400 OP 404 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/266388.266515 DO https://dl.acm.org/doi/10.5555/266388.266515 SF ELIB - SuUB Bremen
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