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1
Automatic decomposition for sequential equivalence checking..:
, In:
Proceedings of the Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.
,
Vasudevan, S.
;
Abraham, J. A.
;
Viswanath, V.
. - p. 71-80 , 2006
Link:
https://dl.acm.org/doi/10.1109/MEMCOD.2006.1695903
RT T1
Proceedings of the Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings.
: T1
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
UL https://suche.suub.uni-bremen.de/peid=acm-2674356&Exemplar=1&LAN=DE A1 Vasudevan, S. A1 Abraham, J. A. A1 Viswanath, V. A1 Jiajin Tu PB IEEE Computer Society YR 2006 K1 SAT solver, automatic decomposition, sequential equivalence checking, register transfer level descriptions, system level description, systems on chip, equivalence checking problem, nominal mapping, functional mapping, system level language, hardware description language SP 71 OP 80 LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/MEMCOD.2006.1695903 DO https://dl.acm.org/doi/10.1109/MEMCOD.2006.1695903 SF ELIB - SuUB Bremen
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