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Recycled error bits : energy-efficient architectural sup..:

, In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis,

Nathan, Ralph ; Anthonio, Bryan ; Lu, Shih-Lien... - p. 117-127 , 2014

Link: https://dl.acm.org/doi/10.1109/SC.2014.15

RT 
T1 <cTitle>Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis</cTitle>: T1 <Title>Recycled error bits				: energy-efficient architectural support for floating point accuracy</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-2683607&Exemplar=1&LAN=DE
				
A1 Nathan, Ralph
A1 Anthonio, Bryan
A1 Lu, Shih-Lien
A1 Naeimi, Helia
A1 Sorin, Daniel J.
A1 Sun, Xiaobai
PB IEEE Press
YR 2014
K1 innovative hardware/software co-design
K1 linear and nonlinear systems
K1 numerical methods
K1 Networks
K1 Network performance evaluation
K1 General and reference
K1 Cross-computing tools and techniques
K1 Performance
K1 Computer systems organization
K1 Dependable and fault-tolerant systems and networks
K1 Hardware
K1 Hardware validation
K1 Integrated circuits
K1 Logic circuits
K1 Arithmetic and datapath circuits
SP 117
OP 127
LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/SC.2014.15
DO https://dl.acm.org/doi/10.1109/SC.2014.15
SF ELIB - SuUB Bremen

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