I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Improving worst-case cache performance through selective by..:
, In:
Proceedings of the 52nd Annual Design Automation Conference
,
Ismail, Mohamed
;
Lo, Daniel
;
Suh, G. Edward
- p. 1-6 , 2015
Link:
https://dl.acm.org/doi/10.1145/2744769.2744855
RT T1
Proceedings of the 52nd Annual Design Automation Conference
: T1
Improving worst-case cache performance through selective bypassing and register-indexed cache
UL https://suche.suub.uni-bremen.de/peid=acm-2744855&Exemplar=1&LAN=DE A1 Ismail, Mohamed A1 Lo, Daniel A1 Suh, G. Edward PB ACM YR 2015 K1 Hardware K1 Hardware validation K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2744769.2744855 DO https://dl.acm.org/doi/10.1145/2744769.2744855 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)