I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
More wires and fewer LUTs : a design methodology for FPG..:
, In:
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
,
Takahara, Atsushi
;
Miyazaki, Toshiaki
;
Murooka, Takahiro
... - p. 12-19 , 1998
Link:
https://dl.acm.org/doi/10.1145/275107.275113
RT T1 <cTitle>Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays</cTitle>: T1 <Title>More wires and fewer LUTs : a design methodology for FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-275113&Exemplar=1&LAN=DE A1 Takahara, Atsushi A1 Miyazaki, Toshiaki A1 Murooka, Takahiro A1 Katayama, Masaru A1 Hayashi, Kazuhiro A1 Tsutsui, Akihiro A1 Ichimori, Takaki A1 Fukami, Ken-nosuke PB ACM YR 1998 K1 Hardware K1 Very large scale integration design K1 Application-specific VLSI designs K1 Hardware test K1 Integrated circuits K1 Electronic design automation K1 Physical design (EDA) K1 Placement K1 Wire routing K1 Hardware validation K1 Robustness SP 12 OP 19 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/275107.275113 DO https://dl.acm.org/doi/10.1145/275107.275113 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
