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1 Ergebnisse
1
Clock domain crossing aware sequential clock gating:
, In:
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition
,
Liu, Jianfeng
;
Hong, Mi-Suk
;
Do, Kyungtae
... - p. 1-6 , 2015
Link:
https://dl.acm.org/doi/10.5555/2755753.2755755
RT T1 <cTitle>Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition</cTitle>: T1 <Title>Clock domain crossing aware sequential clock gating</Title> UL https://suche.suub.uni-bremen.de/peid=acm-2755755&Exemplar=1&LAN=DE A1 Liu, Jianfeng A1 Hong, Mi-Suk A1 Do, Kyungtae A1 Choi, Jung Yun A1 Park, Jaehong A1 Kumar, Mohit A1 Kumar, Manish A1 Tripathi, Nikhil A1 Ranjan, Abhishek PB EDA Consortium YR 2015 K1 clock domain crossing K1 observability K1 power analysis K1 power optimization K1 sequential analysis K1 sequential clock gating K1 sequential optimization K1 stability K1 Hardware K1 Emerging technologies K1 Very large scale integration design K1 Hardware validation K1 Electronic design automation K1 Physical design (EDA) SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2755753.2755755 DO https://dl.acm.org/doi/10.5555/2755753.2755755 SF ELIB - SuUB Bremen
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