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Scheduling instruction effects for a statically pipelined p..:

, In: Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems,

Davis, B. ; Baird, R. ; Gavin, P.... - p. 167-176 , 2015

Link: https://dl.acm.org/doi/10.5555/2830689.2830710

RT 
T1 <cTitle>Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems</cTitle>: T1 <Title>Scheduling instruction effects for a statically pipelined processor</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-2830710&Exemplar=1&LAN=DE
				
A1 Davis, B.
A1 Baird, R.
A1 Gavin, P.
A1 Själander, M.
A1 Finlayson, I.
A1 Rasapour, F.
A1 Cook, G.
A1 Uh, G.-R.
A1 Whalley, D.
A1 Tyson, G.
PB IEEE Press
YR 2015
K1 architecture
K1 compiler
K1 energy
K1 performance
K1 static pipeline
K1 Theory of computation
K1 Design and analysis of algorithms
K1 Approximation algorithms analysis
K1 Scheduling algorithms
K1 Online algorithms
K1 Online learning algorithms
K1 Theory and algorithms for application domains
K1 Machine learning theory
K1 Reinforcement learning
K1 Sequential decision making
K1 Computer systems organization
K1 Embedded and cyber-physical systems
K1 Real-time systems
K1 Architectures
K1 Serial architectures
K1 Pipeline computing
SP 167
OP 176
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/2830689.2830710
DO https://dl.acm.org/doi/10.5555/2830689.2830710
SF ELIB - SuUB Bremen

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