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On How to Accelerate Iterative Stencil Loops : A Scalabl..:

Cattaneo, Riccardo ; Natale, Giuseppe ; Sicignano, Carlo..
ACM Transactions on Architecture and Code Optimization (TACO). 12 (2015) 4 - p. 1-26 , 2015

Link: https://dl.acm.org/doi/10.1145/2842615

RT Journal
T1 <Title>On How to Accelerate Iterative Stencil Loops				: A Scalable Streaming-Based Approach</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-2842615&Exemplar=1&LAN=DE
				
A1 Cattaneo, Riccardo
A1 Natale, Giuseppe
A1 Sicignano, Carlo
A1 Sciuto, Donatella
A1 Santambrogio, Marco Domenico
PB ACM
YR 2015
SN 1544-3566
SN 1544-3973
K1 FPGAs
K1 power efficiency
K1 streaming architectures
K1 Hardware
K1 Electronic design automation
K1 High-level and register-transfer level synthesis
K1 Hardware-software codesign
K1 Methodologies for EDA
K1 Software and its engineering
K1 Software organization and properties
K1 Software system structures
K1 Software architectures
K1 Data flow architectures
K1 Integrated circuits
K1 Logic circuits
K1 Sequential circuits
K1 Theory of computation
K1 Models of computation
K1 Streaming models
K1 Design and analysis of algorithms
K1 Parallel algorithms
K1 Massively parallel algorithms
JF ACM Transactions on Architecture and Code Optimization (TACO)
VO 12
IS 4
SP 1
OP 26
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2842615
DO https://dl.acm.org/doi/10.1145/2842615
SF ELIB - SuUB Bremen

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