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Floorplanning of Partially Reconfigurable Design on Heterog..:
, In:
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Goswami, Pingakshya
;
Bhatia, Dinesh
- p. 275 ff. , 2016
Link:
https://dl.acm.org/doi/10.1145/2847263.2847323
RT T1 <cTitle>Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</cTitle>: T1 <Title>Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only)</Title> UL https://suche.suub.uni-bremen.de/peid=acm-2847323&Exemplar=1&LAN=DE A1 Goswami, Pingakshya A1 Bhatia, Dinesh PB ACM YR 2016 K1 floorplanning K1 heterogeneous fpga K1 partial reconfiguration K1 Hardware K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Electronic design automation K1 Physical design (EDA) K1 Partitioning and floorplanning K1 Programmable logic elements SP 275 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2847263.2847323 DO https://dl.acm.org/doi/10.1145/2847263.2847323 SF ELIB - SuUB Bremen
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