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1 Ergebnisse
1
Development and validation of a hierarchical memory model i..:
, In:
Proceedings of the 1st international workshop on Software and performance
,
Luo, Yong
;
Lubeck, Olaf M.
;
Wasserman, Harvey
.. - p. 152-163 , 1998
Link:
https://dl.acm.org/doi/10.1145/287318.287351
RT T1 <cTitle>Proceedings of the 1st international workshop on Software and performance</cTitle>: T1 <Title>Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model</Title> UL https://suche.suub.uni-bremen.de/peid=acm-287351&Exemplar=1&LAN=DE A1 Luo, Yong A1 Lubeck, Olaf M. A1 Wasserman, Harvey A1 Bassetti, Federico A1 Cameron, Kirk W. PB ACM YR 1998 K1 General and reference K1 Cross-computing tools and techniques K1 Metrics K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Computer systems organization K1 Dependable and fault-tolerant systems and networks K1 Robustness K1 Networks K1 Network performance evaluation K1 Performance SP 152 OP 163 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/287318.287351 DO https://dl.acm.org/doi/10.1145/287318.287351 SF ELIB - SuUB Bremen
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