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Power, Area, and Performance Optimization of Standard Cell ..:

Teman, Adam ; Rossi, Davide ; Meinerzhagen, Pascal..
ACM Transactions on Design Automation of Electronic Systems (TODAES). 21 (2016) 4 - p. 1-25 , 2016

Link: https://dl.acm.org/doi/10.1145/2890498

RT Journal
T1 <Title>Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-2890498&Exemplar=1&LAN=DE
				
A1 Teman, Adam
A1 Rossi, Davide
A1 Meinerzhagen, Pascal
A1 Benini, Luca
A1 Burg, Andreas
PB ACM
YR 2016
SN 1084-4309
SN 1557-7309
K1 Standard cell memories
K1 controlled placement
K1 low power
K1 power-area-performance trade-off
K1 subthreshold operation
K1 Hardware
K1 Integrated circuits
K1 Semiconductor memory
K1 Static memory
K1 Power and energy
K1 Power estimation and optimization
K1 Circuits power issues
K1 Electronic design automation
K1 Physical design (EDA)
K1 Partitioning and floorplanning
K1 Logic circuits
K1 Sequential circuits
K1 Placement
K1 Timing analysis
K1 Static timing analysis
K1 Methodologies for EDA
K1 Best practices for EDA
K1 Emerging technologies
K1 Memory and dense storage
K1 Very large scale integration design
K1 Standard cell libraries
JF ACM Transactions on Design Automation of Electronic Systems (TODAES)
VO 21
IS 4
SP 1
OP 25
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2890498
DO https://dl.acm.org/doi/10.1145/2890498
SF ELIB - SuUB Bremen

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