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Modeling and Study of Two-BDT-Nanostructure based Sequentia..:
, In:
Proceedings of the 26th edition on Great Lakes Symposium on VLSI
,
Marthi, Poorna
;
Reza, Sheikh Rufsan
;
Hossain, Nazir
... - p. 393-396 , 2016
Link:
https://dl.acm.org/doi/10.1145/2902961.2903001
RT T1
Proceedings of the 26th edition on Great Lakes Symposium on VLSI
: T1
Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits
UL https://suche.suub.uni-bremen.de/peid=acm-2903001&Exemplar=1&LAN=DE A1 Marthi, Poorna A1 Reza, Sheikh Rufsan A1 Hossain, Nazir A1 Millithaler, Jean-François A1 Margala, Martin A1 Iñiguez-de-la-Torre, Ignacio A1 Mateos, Javier A1 González, Tomás PB ACM YR 2016 K1 ballistic deflection transistors (BDTs) K1 d-flip flop (DFF) K1 monte carlo (MC) simulations K1 verilog-ams model. K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Non-volatile memory SP 393 OP 396 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2902961.2903001 DO https://dl.acm.org/doi/10.1145/2902961.2903001 SF ELIB - SuUB Bremen
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