I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
A New Approach to Automatic Memory Banking using Trace-Base..:
, In:
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Zhou, Yuan
;
Al-Hawaj, Khalid Musa
;
Zhang, Zhiru
- p. 179-188 , 2017
Link:
https://dl.acm.org/doi/10.1145/3020078.3021734
RT T1
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
: T1
A New Approach to Automatic Memory Banking using Trace-Based Address Mining
UL https://suche.suub.uni-bremen.de/peid=acm-3021734&Exemplar=1&LAN=DE A1 Zhou, Yuan A1 Al-Hawaj, Khalid Musa A1 Zhang, Zhiru PB ACM YR 2017 K1 FPGAs K1 combinatorial optimization K1 compiler optimization K1 data mining K1 high-level synthesis K1 memory systems K1 reconfigurable computing K1 Theory of computation K1 Design and analysis of algorithms K1 Graph algorithms analysis K1 General and reference K1 Cross-computing tools and techniques K1 Experimentation K1 Document types K1 General conference proceedings K1 Hardware K1 Hardware validation K1 Functional verification K1 Theorem proving and SAT solving K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Hardware-software codesign K1 Mathematics of computing K1 Discrete mathematics K1 Graph theory K1 Graph coloring K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Hardware accelerators K1 Mathematical optimization K1 Discrete optimization K1 Optimization with randomized search heuristics K1 Evolutionary algorithms K1 Verification K1 Computer systems organization K1 Architectures K1 Serial architectures K1 Pipeline computing K1 Emerging technologies K1 Memory and dense storage K1 Datapath optimization K1 Theory and algorithms for application domains K1 Machine learning theory K1 Other architectures K1 Reconfigurable computing K1 Graph algorithms K1 Combinatorics K1 Combinatoric problems K1 Simulated annealing SP 179 OP 188 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3020078.3021734 DO https://dl.acm.org/doi/10.1145/3020078.3021734 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)