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1
Quality-Time Tradeoffs in Component-Specific Mapping : H..:
, In:
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Giesen, Hans
;
Rubin, Raphael
;
Gojman, Benjamin
. - p. 85-94 , 2017
Link:
https://dl.acm.org/doi/10.1145/3020078.3026124
RT T1
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
: T1
Quality-Time Tradeoffs in Component-Specific Mapping : How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays
UL https://suche.suub.uni-bremen.de/peid=acm-3026124&Exemplar=1&LAN=DE A1 Giesen, Hans A1 Rubin, Raphael A1 Gojman, Benjamin A1 DeHon, André PB ACM YR 2017 K1 FPGA K1 component-specific mapping K1 variation K1 Hardware K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Robustness K1 Design for manufacturability K1 Process variations K1 Hardware test K1 Design for testability K1 Online test and diagnostics SP 85 OP 94 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3020078.3026124 DO https://dl.acm.org/doi/10.1145/3020078.3026124 SF ELIB - SuUB Bremen
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