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Adapting cache line size to application behavior:

, In: Proceedings of the 13th international conference on Supercomputing,

Veidenbaum, Alexander V. ; Tang, Weiyu ; Gupta, Rajesh.. - p. 145-154 , 1999

Link: https://dl.acm.org/doi/10.1145/305138.305188

RT 
T1 <cTitle>Proceedings of the 13th international conference on Supercomputing</cTitle>: T1 <Title>Adapting cache line size to application behavior</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-305188&Exemplar=1&LAN=DE
				
A1 Veidenbaum, Alexander V.
A1 Tang, Weiyu
A1 Gupta, Rajesh
A1 Nicolau, Alexandru
A1 Ji, Xiaomei
PB ACM
YR 1999
K1 Hardware
K1 Integrated circuits
K1 Semiconductor memory
K1 Dynamic memory
K1 Computing methodologies
K1 Modeling and simulation
K1 Simulation types and techniques
K1 Massively parallel and high-performance simulations
K1 Computer systems organization
K1 Architectures
K1 Serial architectures
K1 Superscalar architectures
K1 Dependable and fault-tolerant systems and networks
K1 Parallel architectures
K1 Multicore architectures
K1 Networks
K1 Network performance evaluation
K1 General and reference
K1 Cross-computing tools and techniques
K1 Performance
K1 Software and its engineering
K1 Software organization and properties
K1 Software system structures
K1 Distributed systems organizing principles
K1 Grid computing
K1 Distributed architectures
SP 145
OP 154
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/305138.305188
DO https://dl.acm.org/doi/10.1145/305138.305188
SF ELIB - SuUB Bremen

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