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1 Ergebnisse
1
HLS Compilation for CPU Interlays:
, In:
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
,
Ordaz, Jose Raul Garcia
;
Koch, Dirk
- p. 1-6 , 2017
Link:
https://dl.acm.org/doi/10.1145/3120895.3120922
RT T1 <cTitle>Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</cTitle>: T1 <Title>HLS Compilation for CPU Interlays</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3120922&Exemplar=1&LAN=DE A1 Ordaz, Jose Raul Garcia A1 Koch, Dirk PB ACM YR 2017 SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3120895.3120922 DO https://dl.acm.org/doi/10.1145/3120895.3120922 SF ELIB - SuUB Bremen
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