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Transactions in relaxed memory architectures:
Dongol, Brijesh
;
Jagadeesan, Radha
;
Riely, James
Proceedings of the ACM on Programming Languages. 2 (2017) POPL - p. 1-29 , 2017
Link:
https://dl.acm.org/doi/10.1145/3158106
RT Journal T1
Transactions in relaxed memory architectures
UL https://suche.suub.uni-bremen.de/peid=acm-3158106&Exemplar=1&LAN=DE A1 Dongol, Brijesh A1 Jagadeesan, Radha A1 Riely, James PB ACM YR 2017 SN 2475-1421 K1 Hardware Transactional Memory K1 Relaxed Memory Models K1 Theory of computation K1 Semantics and reasoning K1 Program reasoning K1 Abstraction K1 Models of computation K1 Concurrency K1 Parallel computing models JF Proceedings of the ACM on Programming Languages VO 2 IS POPL SP 1 OP 29 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3158106 DO https://dl.acm.org/doi/10.1145/3158106 SF ELIB - SuUB Bremen
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