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1 Ergebnisse
1
Automatic layout algorithms for function blocks of CMOS gat..:
, In:
Proceedings of the 22nd ACM/IEEE Design Automation Conference
,
Noda, Shigeo
;
Yoshizawa, Hitoshi
;
Fukuda, Etsuko
... - p. 46-52 , 1985
Link:
https://dl.acm.org/doi/10.5555/317825.317832
RT T1
Proceedings of the 22nd ACM/IEEE Design Automation Conference
: T1
Automatic layout algorithms for function blocks of CMOS gate arrays
UL https://suche.suub.uni-bremen.de/peid=acm-317832&Exemplar=1&LAN=DE A1 Noda, Shigeo A1 Yoshizawa, Hitoshi A1 Fukuda, Etsuko A1 Kato, Haruo A1 Kawanishi, Hiroshi A1 Fujii, Takashi PB IEEE Press YR 1985 K1 Hardware K1 Very large scale integration design K1 Application-specific VLSI designs K1 Electronic design automation K1 Physical design (EDA) K1 Wire routing K1 Partitioning and floorplanning K1 Placement SP 46 OP 52 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/317825.317832 DO https://dl.acm.org/doi/10.5555/317825.317832 SF ELIB - SuUB Bremen
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