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1 Ergebnisse
1
A Hybrid Approach to Equivalent Fault Identification for Ve..:
, In:
Proceedings of the 2018 on Great Lakes Symposium on VLSI
,
Wu, Chia-Cheng
;
Lee, Tung-Yuan
;
Lai, Yung-An
... - p. 447-450 , 2018
Link:
https://dl.acm.org/doi/10.1145/3194554.3194635
RT T1 <cTitle>Proceedings of the 2018 on Great Lakes Symposium on VLSI</cTitle>: T1 <Title>A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3194635&Exemplar=1&LAN=DE A1 Wu, Chia-Cheng A1 Lee, Tung-Yuan A1 Lai, Yung-An A1 Wang, Hsin-Pei A1 Ji, De-Xuan A1 Chang, Yan-Ping A1 Wang, Teng-Chia A1 Liu, Chin-Heng A1 Wang, Chun-Yao A1 Chen, Yung-Chih PB ACM YR 2018 K1 equivalent fault identification K1 fault injection K1 mandatory assignment (MA) K1 verification environment qualification K1 Hardware K1 Hardware test K1 Fault models and test metrics K1 Test-pattern generation and fault simulation K1 Hardware validation K1 Functional verification K1 Equivalence checking SP 447 OP 450 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3194554.3194635 DO https://dl.acm.org/doi/10.1145/3194554.3194635 SF ELIB - SuUB Bremen
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