I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Low Voltage Clock Tree Synthesis with Local Gate Clusters:
, In:
Proceedings of the 2019 Great Lakes Symposium on VLSI
,
Sitik, Can
;
Liu, Weicheng
;
Taskin, Baris
. - p. 99-104 , 2019
Link:
https://dl.acm.org/doi/10.1145/3299874.3318004
RT T1 <cTitle>Proceedings of the 2019 Great Lakes Symposium on VLSI</cTitle>: T1 <Title>Low Voltage Clock Tree Synthesis with Local Gate Clusters</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3318004&Exemplar=1&LAN=DE A1 Sitik, Can A1 Liu, Weicheng A1 Taskin, Baris A1 Salman, Emre PB ACM YR 2019 K1 clock gating K1 clock tree synthesis K1 interconnects K1 low power K1 low voltage K1 Hardware K1 Very large scale integration design K1 Analog and mixed-signal circuits K1 Clock generation and timing K1 Electronic design automation K1 Physical design (EDA) K1 Clock-network synthesis K1 Power and energy K1 Power estimation and optimization K1 Interconnect power issues SP 99 OP 104 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3299874.3318004 DO https://dl.acm.org/doi/10.1145/3299874.3318004 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
