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Design and Evaluation of DNU-Tolerant Registers for Resilie..:
, In:
Proceedings of the 2019 Great Lakes Symposium on VLSI
,
Alghareb, Faris S.
;
DeMara, Ronald F.
- p. 303-306 , 2019
Link:
https://dl.acm.org/doi/10.1145/3299874.3318023
RT T1
Proceedings of the 2019 Great Lakes Symposium on VLSI
: T1
Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage
UL https://suche.suub.uni-bremen.de/peid=acm-3318023&Exemplar=1&LAN=DE A1 Alghareb, Faris S. A1 DeMara, Ronald F. PB ACM YR 2019 K1 datapath resilience K1 pipeline registers K1 reliability K1 soft errors K1 Hardware K1 Robustness K1 Fault tolerance K1 System-level fault tolerance K1 Hardware reliability K1 Circuit hardening K1 Transient errors and upsets K1 Integrated circuits K1 Logic circuits K1 Sequential circuits K1 Error detection and error correction K1 Redundancy SP 303 OP 306 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3299874.3318023 DO https://dl.acm.org/doi/10.1145/3299874.3318023 SF ELIB - SuUB Bremen
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