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Theoretical limits for signal reflections due to inductance..:

, In: Proceedings of the 2000 international workshop on System-level interconnect prediction,

Deschacht, D. ; Servel, G. ; Huret, F... - p. 55-60 , 2000

Link: https://dl.acm.org/doi/10.1145/333032.333033

RT 
T1 <cTitle>Proceedings of the 2000 international workshop on System-level interconnect prediction</cTitle>: T1 <Title>Theoretical limits for signal reflections due to inductance for on-chip interconnections</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-333033&Exemplar=1&LAN=DE
				
A1 Deschacht, D.
A1 Servel, G.
A1 Huret, F.
A1 Paleczny, E.
A1 Kennis, P.
PB ACM
YR 2000
K1 Computer systems organization
K1 Architectures
K1 Parallel architectures
K1 Interconnection architectures
K1 Computing methodologies
K1 Modeling and simulation
K1 Model development and analysis
K1 Model verification and validation
K1 Hardware
K1 Integrated circuits
K1 Interconnect
K1 Networks
K1 Network performance evaluation
K1 General and reference
K1 Cross-computing tools and techniques
K1 Performance
K1 Dependable and fault-tolerant systems and networks
K1 Very large scale integration design
K1 Simulation evaluation
SP 55
OP 60
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/333032.333033
DO https://dl.acm.org/doi/10.1145/333032.333033
SF ELIB - SuUB Bremen

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