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Breaking master-slave model between host and FPGAs:
, In:
Proceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
,
Bosch, Jaume
;
Vidal, Miquel
;
Filgueras, Antonio
... - p. 419-420 , 2020
Link:
https://dl.acm.org/doi/10.1145/3332466.3374545
RT T1 <cTitle>Proceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming</cTitle>: T1 <Title>Breaking master-slave model between host and FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3374545&Exemplar=1&LAN=DE A1 Bosch, Jaume A1 Vidal, Miquel A1 Filgueras, Antonio A1 Álvarez, Carlos A1 Jiménez-González, Daniel A1 Martorell, Xavier A1 Ayguadé, Eduard PB ACM YR 2020 K1 FPGA K1 OmpSs K1 OpenMP K1 heterogeneous computing K1 runtime K1 task-based parallelism K1 Computer systems organization K1 Architectures K1 Other architectures K1 Heterogeneous (hybrid) systems K1 Computing methodologies K1 Parallel computing methodologies K1 Parallel programming languages SP 419 OP 420 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3332466.3374545 DO https://dl.acm.org/doi/10.1145/3332466.3374545 SF ELIB - SuUB Bremen
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