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Architectural Enhancements in Intel® Agilex™ FPGAs:
, In:
Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Chromczak, Jeffrey
;
Wheeler, Mark
;
Chiasson, Charles
... - p. 140-149 , 2020
Link:
https://dl.acm.org/doi/10.1145/3373087.3375308
RT T1 <cTitle>Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</cTitle>: T1 <Title>Architectural Enhancements in Intel® Agilex™ FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3375308&Exemplar=1&LAN=DE A1 Chromczak, Jeffrey A1 Wheeler, Mark A1 Chiasson, Charles A1 How, Dana A1 Langhammer, Martin A1 Vanderhoek, Tim A1 Zgheib, Grace A1 Ganusov, Ilya PB ACM YR 2020 K1 clock skew scheduling K1 dsp K1 fpga K1 logic module K1 routing K1 Hardware K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Programmable logic elements K1 Programmable interconnect K1 Hardware accelerators K1 Reconfigurable logic applications SP 140 OP 149 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3373087.3375308 DO https://dl.acm.org/doi/10.1145/3373087.3375308 SF ELIB - SuUB Bremen
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