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1
High Density Pipelined 8bit Multiplier Systolic Arrays for ..:
, In:
Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Langhammer, Martin
;
Gribok, Sergey
;
Baeckler, Gregg
- p. 322 ff. , 2020
Link:
https://dl.acm.org/doi/10.1145/3373087.3375352
RT T1 <cTitle>Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</cTitle>: T1 <Title>High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3375352&Exemplar=1&LAN=DE A1 Langhammer, Martin A1 Gribok, Sergey A1 Baeckler, Gregg PB ACM YR 2020 K1 array K1 fpga K1 int8 K1 multiplier K1 Hardware K1 Integrated circuits K1 Logic circuits K1 Arithmetic and datapath circuits K1 Reconfigurable logic and FPGAs K1 Hardware accelerators SP 322 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3373087.3375352 DO https://dl.acm.org/doi/10.1145/3373087.3375352 SF ELIB - SuUB Bremen
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