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Reconfigurable tiles of computing-in-memory SRAM architectu..:
, In:
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
,
Gauchi, R.
;
Egloff, V.
;
Kooli, M.
... - p. 121-126 , 2020
Link:
https://dl.acm.org/doi/10.1145/3370748.3406550
RT T1
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
: T1
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization
UL https://suche.suub.uni-bremen.de/peid=acm-3406550&Exemplar=1&LAN=DE A1 Gauchi, R. A1 Egloff, V. A1 Kooli, M. A1 Noel, J.-P. A1 Giraud, B. A1 Vivet, P. A1 Mitra, S. A1 Charles, H.-P. PB ACM YR 2020 K1 PolyBench K1 SIMD K1 SRAM K1 computing-in-memory K1 instruction set simulator K1 system-C/TLM SP 121 OP 126 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3370748.3406550 DO https://dl.acm.org/doi/10.1145/3370748.3406550 SF ELIB - SuUB Bremen
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