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1 Ergebnisse
1
Design Automation Methodology from RTL to Gate-level Netlis..:
, In:
Proceedings of the 2020 on Great Lakes Symposium on VLSI
,
Fu, Rongliang
;
Zhang, Zhi-Min
;
Tang, Guang-Ming
... - p. 145-150 , 2020
Link:
https://dl.acm.org/doi/10.1145/3386263.3406898
RT T1 <cTitle>Proceedings of the 2020 on Great Lakes Symposium on VLSI</cTitle>: T1 <Title>Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3406898&Exemplar=1&LAN=DE A1 Fu, Rongliang A1 Zhang, Zhi-Min A1 Tang, Guang-Ming A1 Huang, Junying A1 Ye, Xiao-Chun A1 Fan, Dong-Rui A1 Sun, Ning-Hui PB ACM YR 2020 K1 RSFQ K1 design automation K1 layer assignment K1 logic synthesis K1 schematic generation K1 superconducting logic circuits K1 Hardware K1 Electronic design automation K1 Logic synthesis K1 Emerging technologies K1 Circuit substrates K1 Superconducting circuits K1 Methodologies for EDA K1 Software tools for EDA SP 145 OP 150 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3386263.3406898 DO https://dl.acm.org/doi/10.1145/3386263.3406898 SF ELIB - SuUB Bremen
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