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Reliability-Enhanced Circuit Design Flow Based on Approxima..:

, In: Proceedings of the 2020 on Great Lakes Symposium on VLSI,

Zhang, Zuodong ; Wang, Runsheng ; Zhang, Zhe... - p. 71-76 , 2020

Link: https://dl.acm.org/doi/10.1145/3386263.3406926

RT 
T1 <cTitle>Proceedings of the 2020 on Great Lakes Symposium on VLSI</cTitle>: T1 <Title>Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-3406926&Exemplar=1&LAN=DE
				
A1 Zhang, Zuodong
A1 Wang, Runsheng
A1 Zhang, Zhe
A1 Huang, Ru
A1 Meng, Chang
A1 Qian, Weikang
A1 Zhou, Zhuangzhuang
PB ACM
YR 2020
K1 aging
K1 approximate computing
K1 circuit reliability simulation
K1 guardband
K1 logic synthesis
K1 negative bias temperature instability (NBTI)
K1 reliability-enhanced design
K1 statistical static timing analysis (SSTA)
K1 Hardware
K1 Robustness
K1 Hardware reliability
K1 Aging of circuits and systems
K1 Theory of computation
K1 Design and analysis of algorithms
K1 Approximation algorithms analysis
K1 Electronic design automation
K1 Timing analysis
K1 Statistical timing analysis
SP 71
OP 76
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3386263.3406926
DO https://dl.acm.org/doi/10.1145/3386263.3406926
SF ELIB - SuUB Bremen

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