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1 Ergebnisse
1
FPGA-based low-batch training accelerator for modern CNNs f..:
, In:
Proceedings of the 39th International Conference on Computer-Aided Design
,
Venkataramanaiah, Shreyas K.
;
Suh, Han-Sok
;
Yin, Shihui
... - p. 1-8 , 2020
Link:
https://dl.acm.org/doi/10.1145/3400302.3415643
RT T1
Proceedings of the 39th International Conference on Computer-Aided Design
: T1
FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory
UL https://suche.suub.uni-bremen.de/peid=acm-3415643&Exemplar=1&LAN=DE A1 Venkataramanaiah, Shreyas K. A1 Suh, Han-Sok A1 Yin, Shihui A1 Nurvitadhi, Eriko A1 Dasu, Aravind A1 Cao, Yu A1 Seo, Jae-sun PB ACM YR 2020 K1 FPGA K1 back-propagation K1 convolutional neural networks K1 hardware accelerator K1 neural network training K1 Hardware K1 Very large scale integration design K1 Application-specific VLSI designs K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Hardware accelerators SP 1 OP 8 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3400302.3415643 DO https://dl.acm.org/doi/10.1145/3400302.3415643 SF ELIB - SuUB Bremen
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