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A RISC-V Simulator and Benchmark Suite for Designing and Ev..:
Ramírez, Cristóbal
;
Hernández, César Alejandro
;
Palomar, Oscar
...
ACM Transactions on Architecture and Code Optimization (TACO). 17 (2020) 4 - p. 1-30 , 2020
Link:
https://dl.acm.org/doi/10.1145/3422667
RT Journal T1 <Title>A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3422667&Exemplar=1&LAN=DE A1 Ramírez, Cristóbal A1 Hernández, César Alejandro A1 Palomar, Oscar A1 Unsal, Osman A1 Ramírez, Marco Antonio A1 Cristal, Adrián PB ACM YR 2020 SN 1544-3566 SN 1544-3973 K1 High-performance computer architecture K1 benchmarking K1 gem5 K1 vector architectures K1 vectorization K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Single instruction, multiple data K1 Computing methodologies K1 Modeling and simulation K1 Simulation support systems K1 Simulation tools JF ACM Transactions on Architecture and Code Optimization (TACO) VO 17 IS 4 SP 1 OP 30 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3422667 DO https://dl.acm.org/doi/10.1145/3422667 SF ELIB - SuUB Bremen
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