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Extending High-Level Synthesis for Task-Parallel Programs:
, In:
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
,
Chi, Yuze
;
Guo, Licheng
;
Choi, Young-kyu
.. - p. 225 ff. , 2021
Link:
https://dl.acm.org/doi/10.1145/3431920.3439470
RT T1 <cTitle>The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</cTitle>: T1 <Title>Extending High-Level Synthesis for Task-Parallel Programs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3439470&Exemplar=1&LAN=DE A1 Chi, Yuze A1 Guo, Licheng A1 Choi, Young-kyu A1 Wang, Jie A1 Cong, Jason PB ACM YR 2021 K1 field-programmable gate array K1 high-level synthesis K1 task-parallel program K1 Computer systems organization K1 Architectures K1 Other architectures K1 Reconfigurable computing K1 Data flow architectures K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Integrated circuits K1 Reconfigurable logic and FPGAs K1 Hardware accelerators K1 Reconfigurable logic applications K1 High-level language architectures SP 225 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/3431920.3439470 DO https://dl.acm.org/doi/10.1145/3431920.3439470 SF ELIB - SuUB Bremen
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