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Power, performance, area and cost analysis of memory-on-log..:
, In:
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
,
Agnesina, Anthony
;
Brunion, Moritz
;
Kim, Jinwoo
... - p. 1-6 , 2021
Link:
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.950247
RT T1 <cTitle>Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design</cTitle>: T1 <Title>Power, performance, area and cost analysis of memory-on-logic face-to-face bonded 3D processor designs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-3489061&Exemplar=1&LAN=DE A1 Agnesina, Anthony A1 Brunion, Moritz A1 Kim, Jinwoo A1 Garcia-Ortiz, Alberto A1 Milojevic, Dragomir A1 Catthoor, Francky A1 Perumkunnil, Manu A1 Lim, Sung Kyu PB IEEE Press YR 2021 K1 Applied computing K1 Computer systems organization K1 Hardware K1 Physical sciences and engineering K1 Integrated circuits K1 Very large scale integration design K1 Electronic design automation K1 Hardware validation K1 Physical design (EDA) SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502475 DO https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502475 SF ELIB - SuUB Bremen
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